Using error correcting codes for parity purposes

ABSTRACT

Software that provides a subset of error correcting code (ECC) bits to be used for parity purposes. The software performs the following steps: (i) providing, in a data block, a first set of redundant bits adapted to detect and correct errors in the data block, based, at least in part, on a first set of error detection/correction (EDC) requirements; and (ii) providing, within the first set of redundant bits, a first sub-set of parity bit(s) adapted to provide single bit error detection for the data block. The EDC requirements include: (i) a minimum hamming distance, and (ii) the bit(s) in the first set of redundant bits that are not in the first sub-set of parity bit(s) include enough bit(s) to create at least P unique (M-2)-tuples, where P equals the number of bits in the first sub-set of parity bits, and where M equals the minimum hamming distance.

BACKGROUND OF THE INVENTION

The present invention relates generally to the field of error control,and more particularly to the field of error detecting and correctingcodes.

Error control is known. Error control is the detection and/or correctionof data errors to ensure reliable data storage and/or delivery. Errorscan occur due to a number of reasons, including, for example, unreliablestorage hardware, unreliable communication channels, and/or channelnoise such as background radiation. Error detection allows for thedetecting of such errors, while error correction enables reconstructionof the original data to correct the errors.

One known error control scheme is the use of parity bits. A parity bitis a bit that is added to a group of source bits to ensure that thenumber of set bits (that is, bits with value 1) in the outcome is evenor odd. Parity bits can be used to detect one or any other odd number(for example, three, five, etc.) of errors in the output. However, aneven number of error-including bits will make the parity bit appearcorrect even though the data is erroneous. Parity bits are typicallyused in situations where an operation can be repeated in case ofdifficulty, where simply detecting the error is helpful.

Another known error control scheme is the use of error-correcting codes(or ECC). ECC are groups of bits that are added to source bits and areusable for both error detection and error correction. ECC typicallyaccomplish error detection and correction by adding redundancy to thesource bits using an algorithm. The redundant bits in ECC may, forexample, be a complex function of many original source bits. ECC arecommonly used in computers where data corruption cannot be toleratedunder any circumstances, such as, for example, scientific or financialcomputing.

SUMMARY

According to an aspect of the present invention, there is a method,computer program product and/or system that performs the following steps(not necessarily in the following order): (i) providing, in a datablock, a first set of redundant bits adapted to detect and correcterrors in the data block, based, at least in part, on a first set oferror detection/correction (EDC) requirements; and (ii) providing,within the first set of redundant bits, a first sub-set of parity bit(s)adapted to provide single bit error detection for the data block. TheEDC requirements include: (i) a minimum hamming distance representing aminimum number of bits in the data block that must change before thefirst set of redundant bits is no longer able to detect or correcterrors in the data block, and (ii) the bit(s) in the first set ofredundant bits that are not in the first sub-set of parity bit(s)include enough bit(s) to create at least P unique (M-2)-tuples, where Pequals the number of bits in the first sub-set of parity bits, and whereM equals the minimum hamming distance.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram view of a first embodiment of a systemaccording to the present invention;

FIG. 2 is a flowchart showing a first embodiment method performed, atleast in part, by the first embodiment system;

FIG. 3 is a block diagram view of a machine logic (for example,software) portion of the first embodiment system;

FIG. 4 is a flowchart showing a second embodiment performed, at least inpart, by a second embodiment system; and

FIG. 5 is a table view showing information that is generated by andhelpful in understanding embodiments of the present invention.

DETAILED DESCRIPTION

In error control, parity bits allow for the detection of single-biterrors in a data block, while error correction codes (ECC) are typicallydesigned to detect (and many times, correct) larger bit errors. Someembodiments of the present invention combine parity bits with ECC suchthat a subset of ECC bits is also used for parity purposes. This enablessingle-bit error detection via parity bits while also providingadditional error detection/correction via ECC code bits, as needed. ThisDetailed Description section is divided into the following sub-sections:(i) The Hardware and Software Environment; (ii) Example Embodiment;(iii) Further Comments and/or Embodiments; and (iv) Definitions.

I. THE HARDWARE AND SOFTWARE ENVIRONMENT

The present invention may be a system, a method, and/or a computerprogram product. The computer program product may include a computerreadable storage medium (or media) having computer readable programinstructions thereon for causing a processor to carry out aspects of thepresent invention.

The computer readable storage medium can be a tangible device that canretain and store instructions for use by an instruction executiondevice. The computer readable storage medium may be, for example, but isnot limited to, an electronic storage device, a magnetic storage device,an optical storage device, an electromagnetic storage device, asemiconductor storage device, or any suitable combination of theforegoing. A non-exhaustive list of more specific examples of thecomputer readable storage medium includes the following: a portablecomputer diskette, a hard disk, a random access memory (RAM), aread-only memory (ROM), an erasable programmable read-only memory (EPROMor Flash memory), a static random access memory (SRAM), a portablecompact disc read-only memory (CD-ROM), a digital versatile disk (DVD),a memory stick, a floppy disk, a mechanically encoded device such aspunch-cards or raised structures in a groove having instructionsrecorded thereon, and any suitable combination of the foregoing. Acomputer readable storage medium, as used herein, is not to be construedas being transitory signals per se, such as radio waves or other freelypropagating electromagnetic waves, electromagnetic waves propagatingthrough a waveguide or other transmission media (e.g., light pulsespassing through a fiber-optic cable), or electrical signals transmittedthrough a wire.

Computer readable program instructions described herein can bedownloaded to respective computing/processing devices from a computerreadable storage medium or to an external computer or external storagedevice via a network, for example, the Internet, a local area network, awide area network and/or a wireless network. The network may comprisecopper transmission cables, optical transmission fibers, wirelesstransmission, routers, firewalls, switches, gateway computers and/oredge servers. A network adapter card or network interface in eachcomputing/processing device receives computer readable programinstructions from the network and forwards the computer readable programinstructions for storage in a computer readable storage medium withinthe respective computing/processing device.

Computer readable program instructions for carrying out operations ofthe present invention may be assembler instructions,instruction-set-architecture (ISA) instructions, machine instructions,machine dependent instructions, microcode, firmware instructions,state-setting data, or either source code or object code written in anycombination of one or more programming languages, including an objectoriented programming language such as Smalltalk, C++ or the like, andconventional procedural programming languages, such as the “C”programming language or similar programming languages. The computerreadable program instructions may execute entirely on the user'scomputer, partly on the user's computer, as a stand-alone softwarepackage, partly on the user's computer and partly on a remote computeror entirely on the remote computer or server. In the latter scenario,the remote computer may be connected to the user's computer through anytype of network, including a local area network (LAN) or a wide areanetwork (WAN), or the connection may be made to an external computer(for example, through the Internet using an Internet Service Provider).In some embodiments, electronic circuitry including, for example,programmable logic circuitry, field-programmable gate arrays (FPGA), orprogrammable logic arrays (PLA) may execute the computer readableprogram instructions by utilizing state information of the computerreadable program instructions to personalize the electronic circuitry,in order to perform aspects of the present invention.

Aspects of the present invention are described herein with reference toflowchart illustrations and/or block diagrams of methods, apparatus(systems), and computer program products according to embodiments of theinvention. It will be understood that each block of the flowchartillustrations and/or block diagrams, and combinations of blocks in theflowchart illustrations and/or block diagrams, can be implemented bycomputer readable program instructions.

These computer readable program instructions may be provided to aprocessor of a general purpose computer, special purpose computer, orother programmable data processing apparatus to produce a machine, suchthat the instructions, which execute via the processor of the computeror other programmable data processing apparatus, create means forimplementing the functions/acts specified in the flowchart and/or blockdiagram block or blocks. These computer readable program instructionsmay also be stored in a computer readable storage medium that can directa computer, a programmable data processing apparatus, and/or otherdevices to function in a particular manner, such that the computerreadable storage medium having instructions stored therein comprises anarticle of manufacture including instructions which implement aspects ofthe function/act specified in the flowchart and/or block diagram blockor blocks.

The computer readable program instructions may also be loaded onto acomputer, other programmable data processing apparatus, or other deviceto cause a series of operational steps to be performed on the computer,other programmable apparatus or other device to produce a computerimplemented process, such that the instructions which execute on thecomputer, other programmable apparatus, or other device implement thefunctions/acts specified in the flowchart and/or block diagram block orblocks.

The flowchart and block diagrams in the Figures illustrate thearchitecture, functionality, and operation of possible implementationsof systems, methods, and computer program products according to variousembodiments of the present invention. In this regard, each block in theflowchart or block diagrams may represent a module, segment, or portionof instructions, which comprises one or more executable instructions forimplementing the specified logical function(s). In some alternativeimplementations, the functions noted in the block may occur out of theorder noted in the figures. For example, two blocks shown in successionmay, in fact, be executed substantially concurrently, or the blocks maysometimes be executed in the reverse order, depending upon thefunctionality involved. It will also be noted that each block of theblock diagrams and/or flowchart illustration, and combinations of blocksin the block diagrams and/or flowchart illustration, can be implementedby special purpose hardware-based systems that perform the specifiedfunctions or acts or carry out combinations of special purpose hardwareand computer instructions.

An embodiment of a possible hardware and software environment forsoftware and/or methods according to the present invention will now bedescribed in detail with reference to the Figures. FIG. 1 is afunctional block diagram illustrating various portions of networkedcomputers system 100, including: sub-system 102; client sub-systems 104,106, 108, 110, 112; communication network 114; computer 200;communication unit 202; processor set 204; input/output (I/O) interfaceset 206; memory device 208; persistent storage device 210; displaydevice 212; external device set 214; random access memory (RAM) devices230; cache memory device 232; and program 300.

Sub-system 102 is, in many respects, representative of the variouscomputer sub-system(s) in the present invention. Accordingly, severalportions of sub-system 102 will now be discussed in the followingparagraphs.

Sub-system 102 may be a laptop computer, tablet computer, netbookcomputer, personal computer (PC), a desktop computer, a personal digitalassistant (PDA), a smart phone, or any programmable electronic devicecapable of communicating with the client sub-systems via network 114.Program 300 is a collection of machine readable instructions and/or datathat is used to create, manage and control certain software functionsthat will be discussed in detail, below, in the Example Embodimentsub-section of this Detailed Description section.

Sub-system 102 is capable of communicating with other computersub-systems via network 114. Network 114 can be, for example, a localarea network (LAN), a wide area network (WAN) such as the Internet, or acombination of the two, and can include wired, wireless, or fiber opticconnections. In general, network 114 can be any combination ofconnections and protocols that will support communications betweenserver and client sub-systems.

Sub-system 102 is shown as a block diagram with many double arrows.These double arrows (no separate reference numerals) represent acommunications fabric, which provides communications between variouscomponents of sub-system 102. This communications fabric can beimplemented with any architecture designed for passing data and/orcontrol information between processors (such as microprocessors,communications and network processors, etc.), system memory, peripheraldevices, and any other hardware components within a system. For example,the communications fabric can be implemented, at least in part, with oneor more buses.

Memory 208 and persistent storage 210 are computer-readable storagemedia. In general, memory 208 can include any suitable volatile ornon-volatile computer-readable storage media. It is further noted that,now and/or in the near future: (i) external device(s) 214 may be able tosupply, some or all, memory for sub-system 102; and/or (ii) devicesexternal to sub-system 102 may be able to provide memory for sub-system102.

Program 300 is stored in processor set 204. Alternatively, program 300may be located in persistent storage 210 for access and/or execution byone or more of the respective computer processors 204, usually throughone or more memories of memory 208. Persistent storage 210: (i) is atleast more persistent than a signal in transit; (ii) stores the program(including its soft logic and/or data), on a tangible medium (such asmagnetic or optical domains); and (iii) is substantially less persistentthan permanent storage. Alternatively, data storage may be morepersistent and/or permanent than the type of storage provided bypersistent storage 210.

Program 300 may include both machine readable and performableinstructions and/or substantive data (that is, the type of data storedin a database). In this particular embodiment, persistent storage 210includes a magnetic hard disk drive. To name some possible variations,persistent storage 210 may include a solid state hard drive, asemiconductor storage device, read-only memory (ROM), erasableprogrammable read-only memory (EPROM), flash memory, or any othercomputer-readable storage media that is capable of storing programinstructions or digital information.

The media used by persistent storage 210 may also be removable. Forexample, a removable hard drive may be used for persistent storage 210.Other examples include optical and magnetic disks, thumb drives, andsmart cards that are inserted into a drive for transfer onto anothercomputer-readable storage medium that is also part of persistent storage210.

Communications unit 202, in these examples, provides for communicationswith other data processing systems or devices external to sub-system102. In these examples, communications unit 202 includes one or morenetwork interface cards. Communications unit 202 may providecommunications through the use of either or both physical and wirelesscommunications links. Any software modules discussed herein may bedownloaded to a persistent storage device (such as persistent storagedevice 210) through a communications unit (such as communications unit202).

I/O interface set 206 allows for input and output of data with otherdevices that may be connected locally in data communication with servercomputer 200. For example, I/O interface set 206 provides a connectionto external device set 214. External device set 214 will typicallyinclude devices such as a keyboard, keypad, a touch screen, and/or someother suitable input device. External device set 214 can also includeportable computer-readable storage media such as, for example, thumbdrives, portable optical or magnetic disks, and memory cards. Softwareand data used to practice embodiments of the present invention, forexample, program 300, can be stored on such portable computer-readablestorage media. In these embodiments the relevant software may (or maynot) be loaded, in whole or in part, onto persistent storage device 210via I/O interface set 206. I/O interface set 206 also connects in datacommunication with display device 212.

Display device 212 provides a mechanism to display data to a user andmay be, for example, a computer monitor or a smart phone display screen.

The programs described herein are identified based upon the applicationfor which they are implemented in a specific embodiment of theinvention. However, it should be appreciated that any particular programnomenclature herein is used merely for convenience, and thus theinvention should not be limited to use solely in any specificapplication identified and/or implied by such nomenclature.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the invention.The terminology used herein was chosen to best explain the principles ofthe embodiment, the practical application or technical improvement overtechnologies found in the marketplace, or to enable others of ordinaryskill in the art to understand the embodiments disclosed herein.

II. EXAMPLE EMBODIMENT

FIG. 2 shows flowchart 250 depicting a method according to the presentinvention. FIG. 3 shows program 300 for performing at least some of themethod steps of flowchart 250. This method and associated software willnow be discussed, over the course of the following paragraphs, withextensive reference to FIG. 2 (for the method step blocks) and FIG. 3(for the software blocks).

The following paragraphs refer extensively to bits of data containedwithin data blocks. As used herein, a data block (or “block”) is simplymeant to be a sequence of one or more bits that may be read or writtenas a group. In some embodiments, for example, a block may be equal to abyte (eight bits) of data. In other embodiments, a block may be equal tosixty four bits of data. However, this is not meant to be limiting, andembodiments of the present invention may include data blocks of varyinglengths and configurations.

Processing begins at step S255, where bit allocation module (“mod”) 302(see FIG. 3) allocates bits in a data block for error detection and/orcorrection (see FIG. 2). As a result, the data block is divided into twoportions: (i) a payload portion; and (ii) an error detection/correction(EDC) portion. The payload portion includes the original source bits(the “payload bits”) meant to be stored or transmitted, while the EDCportion (also referred to as the “EDC code” and/or the “data protectioncode”) includes the newly allocated error detection and/or correctionbits (also referred to as “redundant bits” and/or “EDC bits”).

The data allocation that takes place during step S255 may be based on anumber of factors, including, for example, desired block length, desiredpayload-to-EDC ratio, and/or desired EDC requirements. In manyembodiments of the present invention, the EDC requirements include thenumber of bit errors the EDC portion is required to be able to detectand/or correct. Or, stated another way, the EDC requirements mayinclude: (i) a minimum number of bit errors detectable by using the EDCbits and (ii) a minimum number of bit errors correctable by using theEDC bits. In these embodiments, the EDC requirements may be representedby a minimum “Hamming distance,” which equals a number of bit positionsthat must change in the data block for the EDC portion to no longer beable to detect and/or correct errors. For further discussion of EDCrequirements and Hamming distances, see the Further Comments and/orEmbodiments sub-section of this Detailed Description.

A simple example embodiment is provided herein to assist in explainingaspects of the present invention. In this simplified example embodiment,a ten-bit data block is provided, with eight bits allocated to errordetection and/or correction, resulting in two payload bits and eight EDCbits. In this embodiment, the payload bits are “1” and “0” (or “10”),and the EDC requirements are that the EDC portion must detect andcorrect at least one bit error. It should be noted that this embodimentis being used for explanatory purposes, and that other embodiments maybe preferred to this simple example embodiment. For a discussion of moredetailed embodiments of the present invention, see the Further Commentsand/or Embodiments sub-section of this Detailed Description.

Processing proceeds to step S260, where EDC mod 304 (see FIG. 3) createsEDC bits (see FIG. 2) by setting the bits of the EDC portion of the datablock to redundantly store enough information about the payload portionto be able to detect and/or correct errors in the payload portion. Manyknown (or to be known in the future) error correcting codes (ECC) may beused for the EDC bits, including, for example: cyclic redundancy checkcodes, Reed-Solomon codes, Hamming codes, low-density parity-checkcodes, checksums, cryptographic hash functions, and/or repetition codes.However, this is not meant to be limiting, and the EDC portion mayinclude any configuration of bits that are adapted to detect and/orcorrect errors in the payload portion. For example, in one embodiment,the EDC portion may be constructed using P unique (M-2)-tuples, where Pequals a parity bit chunk length and M equals a minimum Hammingdistance. For a detailed discussion of this embodiment and of EDC bits,see: (i) the Further Comments and/or Embodiments sub-section of thisDetailed Description; and (ii) the Definitions sub-section of thisDetailed Description.

In the present example embodiment, the EDC bits are created using asimple repetition code: for each bit in the payload portion, the bit isrepeated four additional times in the EDC portion. The first four EDCbits repeat the first payload bit, and the second four (and last four)EDC bits repeat the second payload bit. Therefore, the resulting EDCportion is “11110000” (with the entire data block being “1011110000”).In this embodiment, errors can be detected by looking for differencesbetween the payload bits and their corresponding EDC bits (if any bit isdifferent from the others, there is an error). Additionally, errors canbe corrected by replacing error bits with the value of the prevalent bitin their corresponding payload bit/EDC bit combination. For example, ifthe first payload bit is a “0” and its corresponding EDC bits are“1111”, then the “0” would be replaced by “1”, which is the moreprevalent bit.

Processing proceeds to step S265, where parity bit mod 306 (see FIG. 3)creates parity bits from one or more of the existing EDC bits (see FIG.2). In other words, in this step, mod 306 selects a subset of the EDCbits and uses them for parity purposes. Any known (or to be known in thefuture) parity bit method for providing single bit error detection maybe used, such as even bit parity or odd bit parity. For furtherdiscussion of parity bits, see: (i) the Further Comments and/orEmbodiments sub-section of this Detailed Description; and (ii) theDefinitions sub-section of this Detailed Description.

In the present example embodiment, method 250 uses even bit parity forstep S265, such that the parity bit is a “1” if the payload portioncontains an odd number of “1”s and the parity bit is “0” if the payloadportion contains zero “1”s or an even number of “1”s. In terms oflocation, in the present example embodiment the parity bit is located inthe final bit in the EDC portion. As a result (and because the payloadportion contains an odd number of “1”s), step S265 transforms theoriginal EDC portion of “11110000” into “11110001” (with a resultingdata block of “1011110001”).

It should be noted that in many embodiments of the present invention,the process of replacing some existing EDC bits with parity bits shouldnot render the EDC bits ineffective in their purpose of detecting and/orcorrecting errors in payload bits. Instead, the result of step S265should be EDC bits that are capable of detecting and/or correctingerrors and a sub-set of parity bits that are capable of detecting singlebit errors. In the present example embodiment, for example, the EDCportion still functions on its own as an EDC, despite the fact that thefinal bit has been changed from a zero to a one. In the presentembodiment, this is due to additional redundancy provided by the EDCbits. However, in other embodiments (such as those discussed below inthe Further Comments and/or Embodiments sub-section of this DetailedDescription), the error detecting/correcting properties of the EDCportion may be preserved in other ways.

Processing proceeds to step S270, where determination mod 308 determineswhether to use the parity bits or the EDC bits for a given readoperation, based, at least in part, on a set of data read requirements.The data read requirements may include, for example: (i) the level oferror detection needed; (ii) the level of error correction needed;and/or (iii) whether error correction is needed at all. Furthermore, thedata read requirements may be based on a number of factors, such as, forexample, the circumstances behind the given read operation and/or thetype of data contained in the data block. In some embodiments, forexample, the data read requirements may include the checking of variablelength operands and/or byte shifts. In the present example embodiment,the data is read following a data transfer from one computer to anothercomputer. In this embodiment, to minimize the number of processor cyclesinvolved in the read operation, mod 308 chooses to use the parity bitsfor error detection. If no error is detected, processing for method 250completes. However, if an error is detected, mod 308 may choose tore-read the data block using the EDC bits to correct the error.Alternatively, mod 308 may request that the data be re-sent from thesource computer.

III. FURTHER COMMENTS AND/OR EMBODIMENTS

Some embodiments of the present invention recognize the following facts,potential problems and/or potential areas for improvement with respectto the current state of the art: (i) many existing error controlsolutions rely on parity bits or error correcting codes (ECC), but notboth; (ii) existing parity-based solutions only allow for single-biterror detection, and do not allow for multi-bit error detection and/orerror correction; (iii) existing ECC-based solutions can be veryresource-expensive for short data chunks (for example, byte chunks);(iv) existing ECC-based solutions can be complicated and/or expensive togenerate; and/or (v) using both parity and ECC in combination typicallyrequires more bits than desired.

Some embodiments of the present invention may include one, or more, ofthe following features, characteristics and/or advantages: (i)generating a data protection code (DPC) with two bit error detection andone bit error correction; (ii) providing parity protection of bytechunks to support quick data transfer checking, byte shifts, andvariable length operands; and/or (iii) providing both data transferprotection and long term storage protection with a limited area (or bit)budget.

Many embodiments of the present invention utilize a DPC (also referredto as the “EDC portion” and/or “EDC bits”) that is divided into twogroups of bits: (i) a first group that is generated in the same way asparity bits; and (ii) a second group that is generated such that thecomplete DPC meets error detection/correction requirements in the sameway as an ECC. The DPC of these embodiments is adapted to minimize spaceexpense and reduce build complication. For example, an existing approachof using both parity and ECC (the current state of the art) will resultin 17 bits of parity/ECC for one bit error correction and two bit errordetection on an 8 byte (64 bit) word. The DPC of the present invention,however, only requires 13 bits for the same amount of data and errordetection/correction requirements (8 bits in the first group and 5 bitsin the second group).

In many embodiments of the present invention, the first group (alsoreferred to as the “parity group” or “parity bits”) is adapted to beused in situations where parity bits are sufficient (such as, forexample, operand transfer). Additionally, in these embodiments, paritychecking is built into the DPC processing logic, thereby eliminating theneed for extra parity generators.

The DPC generated and used according to the present invention is adaptedto detect errors in a word in a relatively easy and inexpensive manner.In one example embodiment, an 8 byte (64 bit) word is provided. In thisembodiment, the parity bits require only an 8 way XOR tree forsingle-bit error detection. Additionally, the second group of bits (alsoreferred to as the “ECC group” or “ECC bits”) requires a less than 28way XOR tree for two-bit error detection.

In one embodiment of the present invention, method 400 for creating aDPC with combined parity and ECC is provided (see FIG. 4). Method 400includes a number of variables: (i) word length W; (ii) parity chunklength P; (iii) error correction amount C; and (iv) error detectionamount D. In the present example, W equals 64 bits, P equals 8 bits, Cequals 1 bit, and D equals 2 bits.

Processing begins at step S402, where method 400 determines a minimumHamming distance for the DPC. The minimum Hamming distance representsthe minimum number of bits that would have to change between theoriginal word and an altered word (that is, a word with errors) toprevent the DPC from being able to detect the errors. The minimumHamming distance depends on the values of C (the desired amount of errorcorrection) and D (the desired amount of error detection). Specifically,in the present embodiment, the minimum Hamming distance (M) isrepresented by the equation “M=C+D+1”. As such, in this embodiment, anadditional bit of error detection is provided. In the present example,where C equals 1 and D equals 2, M equals 4.

Processing proceeds to step S404, where method 400 creates the paritybits (or the “first group”) for the DPC. This step is performed usingknown methods for creating parity bits. In the present example, becausethe word length (W) equals 64, and the parity chunk length (P) equals 8,eight parity bits are created (one parity bit for each parity chunk inthe word).

Processing then proceeds to step S406, where method 400 determines anamount of ECC bits (that is, “second group” bits) needed to reach theminimum Hamming distance (M). Because parity bits provide two bits ofHamming distance, the additional amount of Hamming distance needed canbe represented by the equation “M-2” (M minus two). In the presentexample, M equals four bits, so M minus two equals two bits.

Continuing with step S406, when C equals one bit, method 400 determineshow many bits (E) are needed to create at least P unique (M-2)-tuples.In other words, method 400 determines the number of bits (E) required tostore enough (M-2)-bit groupings to protect each bit in a parity chunk.In the present example, because P equals 8 and M equals 2, 8 different2-tuples (2-bit groupings) are needed. Or, stated another way, method400 needs to determine how many bits are needed such that at least 8unique groups of those bits with exactly 2 ones in them can be created.As such, 5 bits are needed (as 4 bits will only allow for 6 uniquegroups of bits with 2 ones in them: 0011, 0101, 0110, 1001, 1010, 1100).

Still referring to step S406, when C is greater than one, method 400must calculate E in a different way. In many embodiments of the presentinvention, a balanced version of P unique (M-2)-tuples is used. Forexample, method 400 may use machine logic to examine all combinations ofpossible bit changes to ensure that the tuples selected can still meetthe desired amount of error correction in C.

Once method 400 determines how many second group bits (E) are needed,processing proceeds to step S408, where E second group bits are created.The second group bits are created in any way that allows them to providethe required error detection/correction for the word to be protected. Insome embodiments, a balanced version of P unique (M-2) tuples are usedfor the second group bits. In one embodiment, each bit in the secondgroup bits is created by calculating a parity bit for a certain sub-setof the bits contained in the entire word. Because each bit in the secondgroup of bits represents the parity of a different combination of bitsin the word, the value of any given bit in the word may be recovered (orcorrected) by performing a certain number of XOR functions on the secondgroup bits.

Once the second group bits have been created, they are added to thefirst group to create the resulting EDC. In the present example, the EDCincludes a total of 13 bits (8 bits in the first group and 5 bits in thesecond group).

Table 500 (see FIG. 5) provides an example of data generated by method400 in an embodiment of the present invention. Specifically: column 502shows the bit number for each bit in a DPC, representing the bit'slocation within the DPC; column 504 shows the group that each particularbit is included in (first group or second group); and column 506 showsexample program instructions for generating each DPC bit. It should benoted that the information contained in table 500 is provided forexample purposes, and that method 400 may be implemented in a variety ofways of equivalent or differing feasibility.

IV. DEFINITIONS

Present invention: should not be taken as an absolute indication thatthe subject matter described by the term “present invention” is coveredby either the claims as they are filed, or by the claims that mayeventually issue after patent prosecution; while the term “presentinvention” is used to help the reader to get a general feel for whichdisclosures herein are believed to potentially be new, thisunderstanding, as indicated by use of the term “present invention,” istentative and provisional and subject to change over the course ofpatent prosecution as relevant information is developed and as theclaims are potentially amended.

Embodiment: see definition of “present invention” above—similar cautionsapply to the term “embodiment.”

and/or: inclusive or; for example, A, B “and/or” C means that at leastone of A or B or C is true and applicable.

Module/Sub-Module: any set of hardware, firmware and/or software thatoperatively works to do some kind of function, without regard to whetherthe module is: (i) in a single local proximity; (ii) distributed over awide area; (iii) in a single proximity within a larger piece of softwarecode; (iv) located within a single piece of software code; (v) locatedin a single storage device, memory or medium; (vi) mechanicallyconnected; (vii) electrically connected; and/or (viii) connected in datacommunication.

Computer: any device with significant data processing and/or machinereadable instruction reading capabilities including, but not limited to:desktop computers, mainframe computers, laptop computers,field-programmable gate array (FPGA) based devices, smart phones,personal digital assistants (PDAs), body-mounted or inserted computers,embedded device style computers, application-specific integrated circuit(ASIC) based devices.

Parity bit: a bit that is added to a group of source bits to ensure,during a read operation, that the number of set bits (that is, bits withvalue 1) is even or odd. Parity bits are typically capable of detecting(but not correcting) one or any other odd number (for example, three,five, etc.) of errors in the source bits.

Error detection/correction (EDC) bit: any bit that, by itself, or aspart of a set of bits, provides error detection/correction capabilitiesother than only the error detection/correction capabilities provided bya parity bit. Some sets of EDC bits, for example, provide more bits oferror detection than the single bit error detection provided by paritybits, and other sets of EDC bits provide error correction in addition todetection. Examples of typical sets of EDC bits include, but are notlimited to: cyclic redundancy check codes, Reed-Solomon codes, Hammingcodes, low-density parity-check codes, checksums, cryptographic hashfunctions, and/or repetition codes.

What is claimed is:
 1. A method comprising: providing, in a data block,a first set of redundant bits adapted to detect and correct errors inthe data block, based, at least in part, on a first set of errordetection/correction (EDC) requirements; and providing, within the firstset of redundant bits, a first sub-set of parity bit(s) adapted toprovide single bit error detection for the data block, wherein the EDCrequirements include: (i) a minimum hamming distance representing aminimum number of bits in the data block that must change before thefirst set of redundant bits is no longer able to detect or correcterrors in the data block, and (ii) the bit(s) in the first set ofredundant bits that are not in the first sub-set of parity bit(s)include enough bit(s) to create at least P unique (M-2)-tuples, where Pequals the number of bits in the first sub-set of parity bits, and whereM equals the minimum hamming distance.
 2. The method of claim 1, furthercomprising: using the entire first set of redundant bits, including thefirst sub-set of parity bit(s), to perform error correction or multi-biterror detection for a read operation performed on the data block,without using the first sub-set of parity bit(s) to perform single biterror detection.
 3. The method of claim 1, further comprising: using thefirst sub-set of parity bit(s) to perform single bit error detection fora read operation performed on the data block.
 4. The method of claim 3,further comprising: upon using the first sub-set of parity bit(s) todetermine an error in the data block, using the first set of redundantbits to correct the error.
 5. The method of claim 1, wherein: the EDCrequirements further include: (i) a minimum number of bit errorsdetectable by using the first set of redundant bits, and (ii) a minimumnumber of bit errors correctable by using the first set of redundantbits.
 6. A computer program product comprising a computer readablestorage medium having stored thereon: program instructions to provide,in a data block, a first set of redundant bits adapted to detect andcorrect errors in the data block, based, at least in part, on a firstset of error detection/correction (EDC) requirements; and programinstructions to provide, within the first set of redundant bits, a firstsub-set of parity bit(s) adapted to provide single bit error detectionfor the data block, wherein the EDC requirements include: (i) a minimumhamming distance representing a minimum number of bits in the data blockthat must change before the first set of redundant bits is no longerable to detect or correct errors in the data block, and (ii) the bit(s)in the first set of redundant bits that are not in the first sub-set ofparity bit(s) include enough bit(s) to create at least P unique(M-2)-tuples, where P equals the number of bits in the first sub-set ofparity bits, and where M equals the minimum hamming distance.
 7. Thecomputer program product of claim 6, further comprising: programinstructions to use the entire first set of redundant bits, includingthe first sub-set of parity bit(s), to perform error correction ormulti-bit error detection for a read operation performed on the datablock, without using the first sub-set of parity bit(s) to performsingle bit error detection.
 8. The computer program product of claim 6,further comprising: program instructions to use the first sub-set ofparity bit(s) to perform single bit error detection for a read operationperformed on the data block.
 9. The computer program product of claim 8,further comprising: program instructions to, upon using the firstsub-set of parity bit(s) to determine an error in the data block, usethe first set of redundant bits to correct the error.
 10. The computerprogram product of claim 6, wherein: the EDC requirements furtherinclude: (i) a minimum number of bit errors detectable by using thefirst set of redundant bits, and (ii) a minimum number of bit errorscorrectable by using the first set of redundant bits.
 11. A computersystem comprising: a processor(s) set; and a computer readable storagemedium; wherein: the processor set is structured, located, connectedand/or programmed to run program instructions stored on the computerreadable storage medium; and the program instructions include: programinstructions to provide, in a data block, a first set of redundant bitsadapted to detect and correct errors in the data block, based, at leastin part, on a first set of error detection/correction (EDC)requirements; and program instructions to provide, within the first setof redundant bits, a first sub-set of parity bit(s) adapted to providesingle bit error detection for the data block, wherein the EDCrequirements include: (i) a minimum hamming distance representing aminimum number of bits in the data block that must change before thefirst set of redundant bits is no longer able to detect or correcterrors in the data block, and (ii) the bit(s) in the first set ofredundant bits that are not in the first sub-set of parity bit(s)include enough bit(s) to create at least P unique (M-2)-tuples, where Pequals the number of bits in the first sub-set of parity bits, and whereM equals the minimum hamming distance.
 12. The computer system of claim11, wherein the program instructions further include: programinstructions to use the entire first set of redundant bits, includingthe first sub-set of parity bit(s), to perform error correction ormulti-bit error detection for a read operation performed on the datablock, without using the first sub-set of parity bit(s) to performsingle bit error detection.
 13. The computer system of claim 11, whereinthe program instructions further include: program instructions to usethe first sub-set of parity bit(s) to perform single bit error detectionfor a read operation performed on the data block.
 14. The computersystem of claim 13, wherein the program instructions further include:program instructions to, upon using the first sub-set of parity bit(s)to determine an error in the data block, use the first set of redundantbits to correct the error.
 15. The computer system of claim 11, wherein:the EDC requirements further include: (i) a minimum number of bit errorsdetectable by using the first set of redundant bits, and (ii) a minimumnumber of bit errors correctable by using the first set of redundantbits.